Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance.
A semiconductor memory device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). The data transfer occurs using a semiconductor property where electrical conductivity changes depending on the environment. The transistor has three regions, i.e., a gate, a source, and a drain. Electric charges are moved between the source and the drain according to a control signal inputted to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region.
In the case where a general transistor is formed on a semiconductor substrate, a method of forming a gate on the semiconductor substrate and doping impurities into both sides of the gate so as to form a source and a drain has been used. As the data storage capacity of a semiconductor memory device increases and the feature width thereof decreases, the size of each unit cell has been gradually decreased. That is, the design rule of the capacitor and the transistor included in the unit cell has been reduced. Thus, as the channel length of a cell transistor is gradually decreased, the short channel effect, Drain Induced Barrier Lower (DIBL), etc. occur in the general transistor thus decreasing operational reliability. By maintaining a threshold voltage such that the cell transistor performs a normal operation, it is possible to solve the phenomena generated by decreased channel length. In general, as the channel of the transistor shortens, the concentration of the impurities doped into a region in which the channel is formed has been increased.
However, if the concentration of the impurities doped into the channel region is increased when the design rule is reduced to 100 nm or less, the electric field of a Storage Node (SN) junction increases, thereby lowering the refresh characteristics of a semiconductor memory device. In order to solve this problem, a cell transistor with a three-dimensional channel structure in which a channel extends in a vertical direction is used such that a relatively long channel length of the cell transistor is maintained even when the design rule is decreased. That is, even when a channel width of a horizontal direction is short, the channel length along a vertical direction is relatively long. Thus, impurity doping concentration may be reduced and deterioration of refresh characteristics can be prevented.
In addition, as the integration degree of the semiconductor device is increased, the distance between a word line coupled to a cell transistor and a bit line coupled to the cell transistor is gradually reduced. As a result, there may arise the shortcoming that parasitic capacitance is increased such that an operation margin of a sense amplifier (sense-amp) that amplifies data transmitted via the bit line is deteriorated, resulting in a negative influence upon operation reliability of the semiconductor device. In order to solve the above-mentioned shortcoming, burying the word line structure such that a word line is formed only in a recess instead of an upper part of the semiconductor substrate has been recently proposed to reduce parasitic capacitance between a bit line and a word line. The buried word line structure forms a conductive material in a recess formed in a semiconductor substrate, and covers an upper part of the conductive material with an insulation film such that the word line is buried in a semiconductor substrate. As a result, the buried word line structure can be electrically isolated from a bit line formed over a semiconductor substrate, including source/drain regions.
However, the buried word line (buried gate) structure has some disadvantages. First, a leakage current caused by a Gate Induced Drain Leakage (GIDL) of a semiconductor device increases between a conductive material (gate electrode) and either an N-type junction or a storage node contact of an active region. Second, refresh characteristics of the whole semiconductor device deteriorate due to the deteriorated GIDL characteristics. In order to substantially prevent an increase in the leakage current caused by such GIDL characteristics, large amounts of conductive material (gate electrode) of the buried word line (buried gate) are etched so that an overlap region between the storage node contact and the conductive material (gate electrode) can be minimized. However, assuming that large amounts of the conductive material (gate electrode) of such a buried word line (buried gate) are etched, the etched conductive material unavoidably increases the resistance of the buried word line (buried gate). Although this can prevent a leakage current caused by GIDL characteristics increasing, it also lowers the speed of the semiconductor device.
FIGS. 1A to 1D are cross-sectional views illustrating a semiconductor device and a method for manufacturing the same according to the conventional art.
Referring to FIGS. 1A and 1B, a pad insulation film (hard mask layer), that is composed of a pad oxide film 110 and a pad nitride film 120, is deposited over a semiconductor substrate 100. Then, a photoresist film (not shown) is deposited and an exposure process is then performed using a mask defining an active region 140. Thereafter, a Spin On Dielectric (SOD) material is buried in a trench 130, which is formed by etching both the exposed pad insulation film and the semiconductor substrate 100, and a planarization etching method, such as a Chemical Mechanical Polishing (CMP) method, is performed until the pad insulation film is exposed, so that a device isolation region 150 defining the active region 140 is formed.
Referring to FIG. 1C, after forming the device isolation region 150, N-type impurities are ion-implanted into the active region 140. After that, a photoresist film (not shown) is formed over the active region 140 and the device isolation region 150, and an exposure process is performed using a mask defining the buried gate, such that an insulation film and a hard mask layer are patterned. Thereafter, the active region 110 and the device isolation region 150 are etched using the patterned hard mask layer as an etch mask, so that a gate region 160 is formed. Preferably, the etch process for forming the gate region 160 may be anisotropically achieved.
Referring to FIG. 1D, a gate oxide film 170 is formed over the gate region 160. A gate electrode material (not shown) is buried in the gate region 160 including the gate oxide film 170, such that the recess gate 180 or the buried gate is completed. Under this structure, a GIDL may be caused due to the overlap between the recess gate 180 and the junction.